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Author/Affiliation: Reshi RazdanOpen AccessArticle
7 Pages, 2,415 KB 
A Case Study on Formal Sequential Equivalence Checking based Hierarchical Flow Setup towards Faster Convergence of Complex SOC Designs
by Anantharaj Thalaimalai Vanaraj and Reshi Razdan
Journal of Engineering Research and Sciences, Volume 3, Issue 8, Page # 21-27, 2024; DOI: 10.55708/js0308003
Abstract: Functional Verification Sign-Off is the crux of the design verification problem faced by latest Silicon Designs on the Simulation/Stimulus Driven and the Formal Verification Platforms. Formal Verification Convergence is a custom specific criterion depending on the success, failure, exhaustiveness and reachability of the verification goals generated and validated by the Formal Tool. One of the… Read More
(This article belongs to the Section Hardware and Architecture – Computer Science (HAC))